Semiconductor devices formed on a silicon on insulator (“SOI”) substrate include a semiconductor substrate (also referred to as a “substrate”) that has a buried insulating layer of oxide that isolates a top layer of silicon (wherein, for instance, active devices are formed) from the underlying substrate. Inasmuch as the portion of the substrate underlying the oxide layer typically is not electrically connected to any other structure (i.e., the underlying substrate is floating), static charges can build up in the substrate during an operation of an integrated circuit constructed thereon. The build up of the static charge may cause a back channel of the semiconductor devices on the silicon on insulator substrate to inadvertently turn on, which can disturb a normal operation of the integrated circuit formed by the semiconductor devices. Several deleterious effects may result from the build up of the static charges including an increase of standby current of the integrated circuit, integrated circuit thermal runaway, and even a malfunction of logic, embedded logic and memory circuits constructed on the silicon on insulator substrate.
To overcome the aforementioned deleterious effects, a contact may be created with the underlying substrate to, in effect, establish a ground connection therefor. One technique to create the contact is to establish a wire bond with an under surface of the integrated circuit at the packaging level. Of course, creating the wire bond connection often requires additional steps and materials in forming the integrated circuit. For example, wire bonding with an under surface of the integrated circuit is typically performed on a circuit by circuit basis thereby leading to a time consuming and expensive process to form an integrated circuit.
Several attempts have been pursued to improve on the wire bonded contacts such as a substrate contact disclosed in U.S. Pat. No. 6,300,666 entitled “Method for Forming a Frontside Contact to the Silicon Substrate of a SOI Wafer in the Presence of Planarized Contact Dielectrics,” to Fechner, et al. (“Fechner”), issued Oct. 9, 2001, which is incorporated herein by reference. Fechner discloses a method of forming a substrate contact as part of the normal processing sequence of constructing an integrated circuit without, in this case, exposing a silicon substrate to a gate etch and further employing a local interconnect to raise the substrate contact to a level above a source/drain area prior to depositing a contact dielectric. (Column 2, lines 3–9).
Whereas the substrate contact of Fechner and other references for that matter provide a significant improvement over the wire bonded contacts with the substrate, there are drawbacks associated with the design thereof. First of all, inasmuch as the substrate contacts are formed in an integrated circuit region of a semiconductor die, certain design rules should be followed in designing and constructing the substrate contacts similar to the substrate contact of Fechner. For instance, design rules between a shallow trench isolation region dummy pattern and the substrate contact constructed on the silicon on insulator substrate should be defined and adhered to. The aforementioned design rules should take into account the chemical-mechanical polishing performance of the shallow trench isolation region due to the impact of the substrate contact on the dummy pattern rule. In short, the design rules add another level of complexity in designing and manufacturing the integrated circuit employing the substrate contact, which is not conducive to more efficient and less costly integrated circuit designs and manufacturing processes. Additionally, the designs and processes to form the substrate contacts akin to Fechner may conflict with semiconductor devices such as metal oxide semiconductor transistors and polycrystalline structures within an integrated circuit region of the semiconductor die thereby further complicating the integrated circuit design and related manufacturing processes thereof.
When constructing integrated circuits, in general, a plurality of the integrated circuits are typically constructed simultaneously on a semiconductor wafer or substrate. As described in U.S. Pat. No. 6,412,786, entitled “Die Seal Ring,” to Pan, issued on Jul. 2, 2002, which is incorporated herein by reference, scribe lines are often employed between adjacent semiconductor dies (embodying the integrated circuits) of the substrate to facilitate separating the integrated circuits by cutting the substrate along the scribe lines. It is possible, however, to induce lateral stress on the substrate during the process of separating the semiconductor dies, thereby affecting the integrated circuits. One approach for solving such a problem is to form a seal ring (also referred to as a “guard ring”) between the scribe line and a peripheral region of the circuitry of the integrated circuit. The stress induced by cutting the substrate is generally obstructed by the seal ring and should not directly impact the integrated circuits embodied in the semiconductor dies located on the substrate.
Seal rings are also employed to provide other benefits in the design and packaging of integrated circuits. For instance, during the design and packaging of the integrated circuits, moisture should be prevented from entering the integrated circuits for a variety of reasons. Moisture can be trapped in oxides and increase the dielectric constant thereof, which affects, for example, metal insulator metal capacitors, gate oxide capacitors, and parasitic interconnect capacitors. Moisture can also create trapped charge centers in gate oxides causing threshold voltage shifts in metal oxide semiconductor transistors embodied in the integrated circuits. Additionally, moisture can create interface states at the silicon and gate oxide interface causing degradation in the transistor lifetime through increased hot electron susceptibility. Moisture can also cause corrosion of metal interconnects, reducing the reliability of the integrated circuit. When trapped in the silicon oxide, moisture reduces the oxide mechanical strength and the oxide becomes more prone to cracking due to tensile stress.
Ionic contaminants can also cause damage to the integrated circuit as the contaminants can diffuse rapidly in the silicon oxide. For instance, ionic contaminants can cause threshold voltage instability in the metal oxide semiconductor transistors, and alter the surface potential of the silicon surface in the vicinity of the ionic contaminants. As described in U.S. Pat. No. 6,492,716, entitled “Seal Ring Structure for IC Containing Integrated Digital/RF/Analog Circuits and Functions,” to Bothra, et al., issued on Dec. 10, 2002, which is incorporated herein by reference, a seal ring is often employed to protect the integrated circuit from moisture degradation and ionic contamination.
Additionally, as integrated circuit speeds increase, seal rings have been incorporated into the device encapsulation to reduce radio frequency interference and signal cross coupling. The seal ring is grounded or connected to a signal ground such as a DC supply line to substantially reduce the affects of the interference. The seal ring may be part of the device packaging and a conductive lid may be connected to the seal ring.
Notwithstanding the specific application and the associated benefits associated therewith, seal rings are often employed in the design, construction and packaging of integrated circuits. Inasmuch as the substrate contacts and seal rings employ additional processes and, moreover, valuable real estate to be incorporated into the design and construction of the integrated circuits, it would be advantageous to further integrate substrate contacts and seal rings in the design of the integrated circuits on a semiconductor die.
Accordingly, what is needed in the art is a semiconductor die (also referred to as a “semiconductor chip”) and related method of constructing the same that incorporates a substrate contact into the structure of the seal ring that improves upon and overcomes the deficiencies of the prior art. Also, inasmuch as the substrate contacts, in general, induce additional processes and design rules to be incorporated into the integrated circuit region of a semiconductor chip, it would be advantageous to incorporate a substrate contact outside an integrated circuit region, especially in semiconductor chips employing a silicon on insulator substrate.